An interactive system and method for testing vehicle electronics systems is disclosed in which various vehicle subsystems are exercised under the control of the tester unit while the performance of associated subsystems are monitored to detect and isolate malfunctions. The tester includes interchangeable program cartridges that can be easily inserted to adapt the unit for a variety of different vehicles and test procedures, and also optional interchangeable input/output cartridges for test procedures in which additional access to or from the tester or peripheral devices is necessary.

The test unit accesses the vehicle's electronics data bus by means of an assembly line diagnostic link, the access being accomplished via a multiplexer that makes it possible to locate faults on the data bus itself. The tester greatly reduces the time and effort necessary to analyze malfunctions in the field, and is considerably more comprehensive than prior test equipment. The diagnostic test unit of claim 2, for an automobile in which the electronics data bus is a ring bus and its associated assembly line diagnostic link has a pair of output terminals, wherein the connecting means is adapted to connect the transceiver with each of said output terminals, including a multiplexer connected to multiplex signals between the transceiver and the two output terminals, whereby automobile systems on the electronics data bus can still be accessed by the transceiver despite a fault on the bus. BACKGROUND OF THE INVENTON 1. Field of the Invention This invention relates to automobile testing equipment and methods, and more particularly to the diagnostic testing of automobile electronics systems.

Description of the Prior Art As the use of electronics to control and perform various automotive functions becomes more prevalent, the quick, accurate and comprehensive testing of automotive electronics systems has grown to be more of a problem. (The term 'automobile' as used herein includes trucks and other vehicles having electronics systems analogous to those found in automobiles.) Currently available field test equipment is generally passive in nature. The testers monitor the outputs of various electronics systems in the automobile for a given operating condition, such as the motor idling, in an attempt to determine the cause of a malfunction. However, it may not be possible to determine the cause of many malfunctions without taking the automobile through a sequence of operating conditions, such as starting the engine and accelerating to a high speed, and simultaneously observing the condition of the electronics systems during the testing sequence. Available testers do not have any convenient mechanism for sequencing an automobile through a variety of operating conditions, and are generally limited in the number of different responses they can observe. The inability to perform comprehensive diagnostic testing of electronics systems at the local site level can result in great inefficiencies.

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For example, it is often difficult to determine whether a particular problem resides in the engine or the transmission. Of transmissions which are shipped back to the factory for correction, the majority are returned with no problem having been located, while in most of the remainder the problem is corrected by a minor adjustment at the factory that could have been made in the field had the proper diagnostic equipment been available.

Another complicating factor in electronics testing is the proliferation of many different electronics systems for different makes of cars, among different models from the same automotive manufacturer, and even annual changes within the same model line. The different electronics systems are generally accompanied by different data formats that limit any particular testing unit to only a relatively small number of vehicles. Stocking a large number of different monitors to accommodate the various makes and models is expensive, inefficient and wasteful.

However, due to the complexity of current electronics systems, it is difficult and sometimes impossible to perform adequate field service without the use of proper electronic testers. The proliferation of different electronics systems is not limited to different makes and models; often the same model car will employ significantly different data formats with each successive model year. This rapidly obsoletes testers which are dedicated to any particular make or model. Another problem is the difficulty in simulating normal driving conditions within the confines of an automotive repair shop, while at the same time monitoring the various electronics systems to determine the location and nature of any malfunctions.

Also, some automotive problems are intermittent and do not show up in a single test run. Current testers do not have the capability of monitoring a vehicle's performance over a long period of time and capturing the status of the various electronics systems when an intermittent malfunction occurs so as to enable effective diagnostic analysis. SUMMARY OF THE INVENTION In view of the above problems associated with the prior art, it is an object of the present invention to provide a novel and improved testing unit and method for automotive electronics systems which provides for both passive monitoring of the various systems, and for the active exercising and control of a particular system and the simultaneous monitoring of associated electronics systems to identify any malfunctions related to the system being tested. Another object is the provision of such a testing unit in a compact, portable package that can be hand held and either kept at a local testing site or allowed to travel with the vehicle. Still another object is the provision of a novel and improved automotive electronics tester which can be easily and inexpensively adapted for use with many different kinds of automobiles having a wide variety of electronic data formats.

A further object is the provision of such a testing unit and associated method for continuously monitoring an automobile during normal use and for activating the unit upon the occurrence of an intermittent malfunction to locate and diagnose the problem.

Publication number US0 A1 Publication type Application Application number US 14/139,864 Publication date Jun 26, 2014 Filing date Dec 23, 2013 Priority date Dec 26, 2012 Publication number 139864, 14139864, US 20 A1, US 2014/181560 A1, US 0 A1, US 0A1, US A1, US A1, US-A1-0, US-A1-, US20A1, US2014/181560A1, US0 A1, US0A1, US A1, USA1 Inventors,,,,,,, Original Assignee,,,,,,, Export Citation,, (4), (5), (9), (1) External Links:. Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed. To reduce power consumption, some systems include processors with the ability to perform at various low power (Cx) states. Each C state may indicate a certain level of functionality and corresponding power state.

For example, C0 may indicate the processor is operating at normal levels, C1 may indicate the processor is not executing instructions but may return to an executing state quickly, C2 may indicate the processor is to maintain all software-visible information but may take longer to return to full executing state, C3 may indicate the processor is asleep but keeps its cache coherent, C6 may indicate much deeper sleep state where caches are flushed, etc. In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Further, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software, firmware, or some combination thereof. Also, the use of “instruction” and “micro-operation” (uop) is interchangeable as discussed herein.

Power management is crucial for mobile devices (such as phones, tablets, UMPC (Ultra-Mobile Personal Computer), laptop computers, etc.) and hence it is critical that such platforms are highly optimized from a power and performance point of view. To this end, some embodiments provide power consumption reduction (e.g., in System on Chip (SOC) platforms) via power state switching Generally, an SOC refers to an integrated circuit chip or die that includes/integrates various components (such as one or more components discussed herein with reference to the figures, such as one or more of: processor core(s), memory, networking logic, etc.) to provide a system. For example, battery life of SOCs (e.g., running the Android™ OS or other operating systems used in mobile devices) may be increased through dynamic power state switching In an embodiment, the power state of a device is dynamically switched between S0ix and S3 during run-time. Generally, “S0ix” refers to improved idle power state(s) achieved by platform-level power management that is event driven (e.g., based on OS or software application input) instead of traditional idle power state that is driven either by a user or based on a determination that a platform has been idle for too long (based on a pre-programmed time). In some embodiments, at least some of the power consumption states discussed herein may be in accordance with or similar to those defined under Advanced Configuration and Power Interface (ACPI) specification, Revision 5, December 2011.

As discussed herein, “S3” generally refers to a power state such as standby, sleep, and/or suspend to Random Access Memory (RAM), e.g., while the RAM remains powered to maintain data correctness. In one embodiment, a processor includes logic (such as logic 120 discussed with reference to the figures herein) to control which specific processor core(s) are to change power states based, at least in part, on input from OS software and/or software application(s). Moreover, the ability to control the level of power states may be used to optimize platform power consumption in response to various determinations such as based on the workload, scenario, usage, etc. Furthermore, at least some OS operations discussed herein may be interchangeably performed by software applications, firmware, etc.

The techniques discussed herein may be used in any type of a processor with performance state settings, such as the processors discussed with reference to FIGS. More particularly, FIG. 1 illustrates a block diagram of a computing system 100, according to an embodiment of the invention.

The system 100 may include one or more processors 102- 1 through 102-N (generally referred to herein as “processors 102” or “processor 102”). The processors 102 may communicate via an interconnection network or bus 104. Each processor may include various components some of which are only discussed with reference to processor 102- 1 for clarity. Accordingly, each of the remaining processors 102- 2 through 102-N may include the same or similar components discussed with reference to the processor 102- 1.

In an embodiment, the processor 102- 1 may include one or more processor cores 106- 1 through 106-M (referred to herein as “cores 106” or more generally as “core 106”), a shared cache 108, a router 110, and/or a processor control logic or unit 120. The processor cores 106 may be implemented on a single integrated circuit (IC) chip.

Moreover, the chip may include one or more shared and/or private caches (such as cache 108), buses or interconnections (such as a bus or interconnection network 112), memory controllers (such as those discussed with reference to FIGS. 9-10), or other components. The shared cache 108 may store data (e.g., including instructions) that are utilized by one or more components of the processor 102- 1, such as the cores 106. For example, the shared cache 108 may locally cache data stored in a memory 114 for faster access by components of the processor 102.

In an embodiment, the cache 108 may include a mid-level cache (such as a level 2 (L2), a level 3 (L3), a level 4 (L4), or other levels of cache), a last level cache (LLC), and/or combinations thereof. Moreover, various components of the processor 102- 1 may communicate with the shared cache 108 directly, through a bus (e.g., the bus 112), and/or a memory controller or hub. As shown in FIG. 1, in some embodiments, one or more of the cores 106 may include a level 1 (L1) cache 116- 1 (generally referred to herein as “L1 cache 116”). In one embodiment, the control unit 120 controls which specific processor core(s) are to change power states (e.g., between S3 and S0ix states) based, at least in part, on input from OS software and/or software application(s) (e.g., that may be stored in the memory 114).

Moreover, the ability to control the level of power states may be used to optimize platform power consumption in response to various determinations such as based on the workload, scenario, usage, etc. Furthermore, at least some OS operations discussed herein may be interchangeably performed by software applications, firmware, etc. 2 illustrates a block diagram of portions of a processor core 106 and other components of a computing system, according to an embodiment of the invention. In one embodiment, the arrows shown in FIG. 2 illustrate the flow direction of instructions through the core 106. One or more processor cores (such as the processor core 106) may be implemented on a single integrated circuit chip (or die) such as discussed with reference to FIG. Moreover, the chip may include one or more shared and/or private caches (e.g., cache 108 of FIG.

1), interconnections (e.g., interconnections 104 and/or 112 of FIG. 1), control units, memory controllers, or other components. As illustrated in FIG. 2, the processor core 106 may include a fetch unit 202 to fetch instructions (including instructions with conditional branches) for execution by the core 106. The instructions may be fetched from any storage devices such as the memory 114 and/or the memory devices discussed with reference to FIGS.

The core 106 may also include a decode unit 204 to decode the fetched instruction. For instance, the decode unit 204 may decode the fetched instruction into a plurality of uops (micro-operations). Additionally, the core 106 may include a schedule unit 206.

The schedule unit 206 may perform various operations associated with storing decoded instructions (e.g., received from the decode unit 204) until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit 206 may schedule and/or issue (or dispatch) decoded instructions to an execution unit 208 for execution. The execution unit 208 may execute the dispatched instructions after they are decoded (e.g., by the decode unit 204) and dispatched (e.g., by the schedule unit 206). In an embodiment, the execution unit 208 may include more than one execution unit. The execution unit 208 may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit 208.

Further, the execution unit 208 may execute instructions out-of-order. Hence, the processor core 106 may be an out-of-order processor core in one embodiment. The core 106 may also include a retirement unit 210. The retirement unit 210 may retire executed instructions after they are committed.

In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. 3 illustrates a block diagram of power management architecture for an Android based system that may be used to implement one or more embodiments discussed herein.

More specifically, the Android power management infrastructure is split across the User space 302 and Kernel layer 304. Wake locks may form a critical part of the framework.

A “Wake Lock” can be defined as request by the application(s) 306 and/or service(s) to request one or more of the platform resources (such as CPU (Central Processing Unit—also referred to herein interchangeably as “processor”), display, etc.), e.g. Herr Der Ringe Schlacht Um Mittelerde 1 Free Download Vollversion there. , to stay powered on or awake (hence, a “wake lock” may also be referred to herein interchangeably as a “awake request”). The Android Framework exposes power management to services and/or applications through a Power Manager class. All calls for Power Management go through the Android runtime Power Manager API (Application Programming Interface) to acquire and release wake locks. Kernel drivers may register with the Android Power Manager driver so that they are notified immediately prior to power down or after power up—drivers can register early_suspend( ) and late_resume( ) handlers, which are called when the display power state changes. The Android OS currently supports only suspend to RAM (a.k.a., S3) state (e.g., while power is supplied to RAM to maintain data correctness).

This builds upon the traditional Linux® power management infrastructure and uses concepts of wake locks (i.e., application hints about platform resource usage) to achieve S3. The power management infrastructure in Android requires that applications and services request CPU resources with “wake locks” through the Android application framework 308 and/or native Linux libraries. If there are no active wake locks, Android will suspend the system to S3. While the current S3 implementation in Android helps reduce overall platform power, this does not satisfy applications that require always connected behavior. Applications like instant messengers, VoIP (Voice over Internet Protocol), etc. Need to send “keep alive” messages to maintain their active sessions.

Entering S3 will result in freezing these applications and therefore connections can timeout and the sessions will have to be re-established on resume. To keep these applications active and still achieve reasonable power numbers, S0ix or Active Idle states feature (also known as Connected Standby in recent Intel®-based Microsoft Windows® platforms) can be used from the platform perspective in some embodiments. As discussed herein, S0ix and Active Idle states are used interchangeably. Some embodiments use S0ix during an idle window to allow the platform to stay in the lowest power state as long as reasonably possible. In this state, all platform components are transitioned to an appropriate lower power state (e.g., CPU is in Cx state, memory is in Self Refresh, other components are clock or power gated, etc.) in accordance with an embodiment.

As soon a timer or wake event occurs, the platform moves into an “Active” state (e.g., only the components that are needed are turned on, keeping everything else still in low power state). Hence, on true idleness, CPU C-states may be extended to devices, and the rest of the platform, e.g., pushing the platform aggressively to S0ix states. Referring to FIG. 4, a timing diagram is shown for aligning platform power states with CPU during device idleness at S0ix, according to an embodiment. As shown, various components such as memory, controllers, clocks, Voltage Regulator(s) (VRs), and other platform components are aligned during an idle window with the CPU, e.g., based on an OS timer (e.g., HPET (High Performance Event Timer)) after some active window, followed by an optional policy windows. Once the idle window ends, and after an optional warm-up window, the active state resumes.

5 is a graph of average power versus time illustrating comparison of how S0ix states impact platform power states, according to an embodiment. More specifically, FIG. 5 illustrates how the impact of S0ix states compares with traditional (e.g., ACPI-based) power management. As shown, even after applications acquire wake locks to prevent S3, OS Power Management (OSPM) driver may still opportunistically cause initiation of S0i3 (which may be more generally referred to herein as S0ix), which may transition afterwards to S3, e.g., when no wake locks remain.

In some implementations, the OS for a smart phone or tablet may implement both S0ix and S3. S0ix may be used in very specific scenarios like low power audio playback (where the entire platform except the audio cluster can be put into a low power mode), or display self-refresh (where only the display panel can be kept on, and entire SOC can be put into lowest possible power state). S0ix has very low entry/exit latencies at about 2 ms, whereas S3 entry/exit latencies range in the order of 100s of milliseconds (since devices must be suspended, applications must be frozen, etc.).

For example, in idle scenarios, when the phone is in idle standby with 3G and/or WLAN (Wireless Local Area Network) connected), the platform power can still be around 14 mW on some Android based phones. Ideally, there should be no wakes on the platform that can cause the phone to exit out of S3 state and into S0 state (where S0 refers to the operating/working state). However, in real usage scenarios, there may be a lot of wakes that happen when background data is enabled on a real network. Most of these wakes may be due to applications waking the platform (such as maps, Google® GSF (Google Services Framework), etc.) or applications performing push from network (such as Google+™, etc.). These wakes could happen every 30 sec (e.g., as seen on real live network with WIFI (Wireless Fidelity) on).

To this end, some embodiments reduce platform power consumption by aggressively invoking and maintaining S0ix state in mobile devices (such as phones, tablets, UMPC (Ultra-Mobile Personal Computer), laptop computers, etc.). Moreover, entering/exiting S3 too frequently may not always provide a net power benefit, e.g., due to the fact that S3 can have higher transition cost of doing full suspend/resume (around 2 seconds) as compared to S0i3 (around 2 ms). In fact, in some situations, entering/exiting S3 too frequently can actually hurt, leading to a higher consumption when selecting S3 if there are frequent wakes happening on the platform. In such scenarios, state S0ix is entered rather than S3 in an embodiment (even if Android power management attempts to enter S3). In some implementations, there may be periodic events due to different applications (such as Google Services, Google Sync, Maps, etc.) that cause the platform to wake up periodically from standby (or S3). For example, some phones may wake up as many as 250 times in an hour (i.e., 4 wakes a minute, or one every 15 seconds). However, as the number of wakes increases, entering S0i3 instead of S3 becomes more and more beneficial.

This is illustrated in FIG. 6 which shows platform current draw (in mA) versus the number of wakes (e.g., per second) changes for S0i3/S3 threshold on a sample platform, according to some embodiments. 8 illustrates a sample suspend flow 800 (e.g., for an Android OS) according to an embodiment. Flow 800 is used to dynamically choose S0ix versus S3 in some embodiments. In some embodiments, various components discussed with reference to FIGS. 1-7 and 9- 10 may be utilized to perform one or more of the operations discussed with reference to FIG.

For example, the control unit 120 may be used to control power consumption states of one or more processor cores 106 and/or perform one or more of the operations discussed with reference to flow 800. As illustrated, whenever a wake lock is taken or released 802, the kernel interface 804 for grabbing a wake lock is accessed at 806. The user mode policy manager for Android will know what locks are held and when there are no full wake locks the power management service will inform the kernel to turn off the display by accessing the /sys/power/state interface, by writing “mem” to it. To turn on the display, the PM (Power Management) service writes “on” to /sys/power/state. This is illustrated in FIG. As it can be seen, there are two main kernel work queues: (1) early suspend work queue (shown on the left portion of the figure including 810- 814): this is invoked from the main kernel path when “mem” is written into /sys/power/state at 818 (this work queue is responsible for calling all drivers that have registered early_suspend notifiers); and (2) suspend work queue (shown on the right portion of the figure including 806 and 820- 822): when there are no wake locks held in the platform, this work queue finally freezes application processes, and invokes the pm_suspend path in the kernel.

Moreover, early suspend happens when the user mode writes “mem” to /sys/power/state at 818. For example, whenever the user mode turns off the screen, the registered early suspend callbacks are called at 812. Setup Camfrog Bot Linux. The kernel keeps a list of wake_locks held. When the wake lock list transitions from non-empty to empty pm_suspend is called at 822. This is a Linux platform state where all applications are frozen, drivers have their suspend entry points called, and interrupts are turned off. The platform will not exit this state except on external event, e.g., GPIO (General Purpose Input/Output), interrupt generated from an RTC (Real Time Clock), or an external interrupt (an incoming call for example). All non-wake-up hardware is expected to enter its lowest power state to reduce power consumption.

Hardware that can generate a wake up interrupt is expected to go into a low power mode as well, but still function enough to wake the system out of the suspend state. Some embodiments are implemented within the Android power management infrastructure, and more specifically within the Linux Kernel. For example, at operation 822, a new embodiment is provided to extend the functionality of an alarm driver to expose information of when the next alarm is expected to be triggered. This newly added function is used by a PMU (Power Management Unit) driver, e.g., along with a programmed threshold value, to determine if the platform should enter S0ix or S3. In this way, a suspend is authorized only when the next alarm expiry is higher than the break event. The updated kernel PM suspend path (as shown in FIG.

8) is able to dynamically pick S0ix or S3 depending on a tunable parameter (which may be set at boot time or run time in various embodiments). 9 illustrates a block diagram of a computing system 900 in accordance with an embodiment of the invention. The computing system 900 may include one or more central processing unit(s) (CPUs) 902 or processors that communicate via an interconnection network (or bus) 904. The processors 902 may include a general purpose processor, a network processor (that processes data communicated over a computer network 903), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors 902 may have a single or multiple core design. The processors 902 with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors 902 with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors.

In an embodiment, one or more of the processors 902 may be the same or similar to the processors 102 of FIG. For example, one or more of the processors 902 may include the control unit 120 discussed with reference to FIGS. Also, the operations discussed with reference to FIGS. 1-8 may be performed by one or more components of the system 900.

A chipset 906 may also communicate with the interconnection network 904. The chipset 906 may include a memory control hub (MCH) 908. The MCH 908 may include a memory controller 910 that communicates with a memory 912 (which may be the same or similar to the memory 114 of FIG. The memory 912 may store data, including sequences of instructions, that may be executed by the CPU 902, or any other device included in the computing system 900. In one embodiment of the invention, the memory 912 may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk.

Additional devices may communicate via the interconnection network 904, such as multiple CPUs and/or multiple system memories. The MCH 908 may also include a graphics interface 914 that communicates with a display device 916. In one embodiment of the invention, the graphics interface 914 may communicate with the display device 916 via an accelerated graphics port (AGP).

In an embodiment of the invention, the display 916 (such as a flat panel display) may communicate with the graphics interface 914 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display 916. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display 916. A hub interface 918 may allow the MCH 908 and an input/output control hub (ICH) 920 to communicate. The ICH 920 may provide an interface to I/O device(s) that communicate with the computing system 900.

The ICH 920 may communicate with a bus 922 through a peripheral bridge (or controller) 924, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. The bridge 924 may provide a data path between the CPU 902 and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH 920, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH 920 may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices. The bus 922 may communicate with an audio device 926, one or more disk drive(s) 928, and a network interface device 930 (which is in communication with the computer network 903). Other devices may communicate via the bus 922.

Also, various components (such as the network interface device 930) may communicate with the MCH 908 in some embodiments of the invention. In addition, the processor 902 and the MCH 908 may be combined to form a single chip. Furthermore, the graphics accelerator 916 may be included within the MCH 908 in other embodiments of the invention. Furthermore, the computing system 900 may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g., 928), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions). In an embodiment, the processors 1002 and 1004 may be one of the processors 902 discussed with reference to FIG.

The processors 1002 and 1004 may exchange data via a point-to-point (PtP) interface 1014 using PtP interface circuits 1016 and 1018, respectively. Also, the processors 1002 and 1004 may each exchange data with a chipset 1020 via individual PtP interfaces 1022 and 1024 using point-to-point interface circuits 1026, 1028, 1030, and 1032. The chipset 1020 may further exchange data with a graphics circuit 1034 via a graphics interface 1036, e.g., using a PtP interface circuit 1037. The chipset 1020 may communicate with a bus 1040 using a PtP interface circuit 1041. The bus 1040 may communicate with one or more devices, such as a bus bridge 1042 and I/O devices 1043. Via a bus 1044, the bus bridge 1042 may communicate with other devices such as a keyboard/mouse 1045, communication devices 1046 (such as modems, network interface devices, or other communication devices that may communicate with the computer network 903), audio I/O device 1047, and/or a data storage device 1048. The data storage device 1048 may store code 1049 that may be executed by the processors 1002 and/or 1004.

In various embodiments of the invention, the operations discussed herein, e.g., with reference to FIGS. 1-10, may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product, e.g., including (e.g., a non-transitory) machine-readable or computer-readable medium having stored thereon instructions (or software procedures) used to program a computer to perform a process discussed herein. The machine-readable medium may include a storage device such as those discussed with respect to FIGS. Also, in the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. In some embodiments of the invention, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other.

“Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

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